发布时间 : 星期一 文章DE2-115所有引脚分配表更新完毕开始阅读04067e4976a20029bc642d27
ENET0_RX_DATA[3] PIN_C15 GMII and MII receive data[3] 2.5V 1 GMII and MII receive data valid 1 2.5V ENET0_RX_DV PIN_C17 ENET0_RX_ER ENET0_TX_CLK PIN_D18 PIN_B17 GMII and MII receive error 1 2.5V MII transmit clock 1 MII transmit data[0] 1 MII transmit data[1] 1 MII transmit data[2] 1 MII transmit data[3] 1 2.5V 2.5V 2.5V 2.5V 2.5V ENET0_TX_DATA[0] PIN_C18 ENET0_TX_DATA[1] PIN_D19 ENET0_TX_DATA[2] PIN_A19 ENET0_TX_DATA[3] PIN_B19 ENET0_TX_EN PIN_A18 GMII and MII transmit enable 2.5V 1 GMII and MII transmit error 1 2 .5V GMII Transmit Clock 2 2.5V ENET0_TX_ER ENET1_GTX_CLK ENET1_INT_N ENET1_LINK100 PIN_B18 PIN_C23 PIN_D24 PIN_D13 Interrupt open drain output 2 2.5V Parallel LED output of 100BASE-TX link 2 Management data clock reference 2 Management data 2 Hardware reset signal 2 2.5V ENET1_MDC PIN_D23 2.5V ENET1_MDIO ENET1_RST_N ENET1_RX_CLK ENET1_RX_COL ENET1_RX_CRS PIN_D25 PIN_D22 PIN_B15 PIN_B22 PIN_D20 2.5V 2.5V GMII and MII receive clock 2 2.5V GMII and MII collision 2 2.5V GMII and MII carrier sense 2 2.5V GMII and MII receive data[0] 2.5V 2 ENET1_RX_DATA[0] PIN_B23 ENET1_RX_DATA[1] PIN_C21 GMII and MII receive data[1] 2.5V 2 GMII and MII receive data[2] 2.5V 2 GMII and MII receive data[3] 2.5V 2 GMII and MII receive data valid 2 2.5V ENET1_RX_DATA[2] PIN_A23 ENET1_RX_DATA[3] PIN_D21 ENET1_RX_DV PIN_A22 ENET1_RX_ER ENET1_TX_CLK PIN_C24 PIN_C22 GMII and MII receive error 2 2.5V MII transmit clock 2 MII transmit data[0] 2 MII transmit data[1] 2 MII transmit data[2] 2 MII transmit data[3] 2 2.5V 2.5V 2.5V 2.5V 2.5V ENET1_TX_DATA[0] PIN_C25 ENET1_TX_DATA[1] PIN_A26 ENET1_TX_DATA[2] PIN_B26 ENET1_TX_DATA[3] PIN_C26 ENET1_TX_EN PIN_B25 GMII and MII transmit enable 2.5V 2 GMII and MII transmit error 2 2.5V Ethernet clock source 3.3V ENET1_TX_ER ENETCLK_25 PIN_A25 PIN_A14 表 15 TV 解码芯片引脚配置
Signal Name FPGA Pin No. Description I/O Standard 3.3V 3.3V 3.3V 3.3V 3.3V TD_ DATA [0] PIN_E8 TD_ DATA [1] PIN_A7 TD_ DATA [2] PIN_D8 TD_ DATA [3] PIN_C7 TD_ DATA [4] PIN_D7 TV Decoder Data[0] TV Decoder Data[1] TV Decoder Data[2] TV Decoder Data[3] TV Decoder Data[4] TD_ DATA [5] PIN_D6 TD_ DATA [6] PIN_E7 TD_ DATA [7] PIN_F7 TD_HS TD_VS TD_CLK27 PIN_E5 PIN_E4 PIN_B14 TV Decoder Data[5] TV Decoder Data[6] TV Decoder Data[7] TV Decoder H_SYNC TV Decoder V_SYNC TV Decoder Clock Input. TV Decoder Reset I2C Clock I2C Data 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V TD_RESET_N PIN_G7 I2C_SCLK I2C_SDAT PIN_B7 PIN_A8 3.3V 3.3V 3.3V 表 16 USB (ISP1362)引脚配置 Signal Name FPGA Pin No. Description I/O Standard 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V OTG_ADDR[0] OTG_ADDR[1] OTG_DATA[0] OTG_DATA[1] OTG_DATA[2] OTG_DATA[3] OTG_DATA[4] OTG_DATA[5] OTG_DATA[6] OTG_DATA[7] OTG_DATA[8] PIN_H7 PIN_C3 PIN_J6 PIN_K4 PIN_J5 PIN_K3 PIN_J4 PIN_J3 PIN_J7 PIN_H6 PIN_H3 ISP1362 Address[0] ISP1362 Address[1] ISP1362 Data[0] ISP1362 Data[1] ISP1362 Data[2] ISP1362 Data[3] ISP1362 Data[4] ISP1362 Data[5] ISP1362 Data[6] ISP1362 Data[7] ISP1362 Data[8] OTG_DATA[9] OTG_DATA[10] OTG_DATA[11] OTG_DATA[12] OTG_DATA[13] OTG_DATA[14] OTG_DATA[15] OTG_CS_N OTG_RD_N OTG_WR_N OTG_RST_N OTG_INT[0] OTG_INT[1] PIN_H4 PIN_G1 PIN_G2 PIN_G3 PIN_F1 PIN_F3 PIN_G4 PIN_A3 PIN_B3 PIN_A4 PIN_C5 PIN_A6 PIN_D5 ISP1362 Data[9] ISP1362 Data[10] ISP1362 Data[11] ISP1362 Data[12] ISP1362 Data[13] ISP1362 Data[14] ISP1362 Data[15] ISP1362 Chip Select ISP1362 Read ISP1362 Write ISP1362 Reset ISP1362 Interrupt 0 ISP1362 Interrupt 1 ISP1362 DMA Acknowledge 0 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V OTG_DACK_N[0] PIN_C4 OTG_DACK_N[1] PIN_D4 OTG_DREQ[0] OTG_DREQ[1] OTG_FSPEED PIN_J1 PIN_B4 PIN_C6 ISP1362 DMA Acknowledge 1 3.3V ISP1362 DMA Request 0 ISP1362 DMA Request 1 3.3V 3.3V USB Full Speed, 0 = Enable, Z 3.3V = Disable USB Low Speed, 0 = Enable, Z 3.3V = Disable OTG_LSPEED PIN_B6 表 17 IR 引脚配置 Signal Name IRDA_RXD FPGA Pin No. Description PIN_Y15 IR Receiver I/O Standard 3.3V