发布时间 : 星期三 文章FPGA读写i2c_verilog更新完毕开始阅读0aaeeb92524de518964b7de0
STOP1: begin if(`SCL_LOW) begin sda_link <= 1'b1; sda_r <= 1'b0; cstate <= STOP1; end else if(`SCL_HIG) begin sda_r <= 1'b1; //scl为高时，sda产生上升沿（结束信号） cstate <= STOP2; end else cstate <= STOP1; end STOP2: begin if(`SCL_LOW) sda_r <= 1'b1; else if(cnt_20ms==20'hffff0) cstate <= IDLE; else cstate <= STOP2; end default: cstate <= IDLE; endcase end
assign sda = sda_link ? sda_r:1'bz; assign dis_data = read_data;
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endmodule