发布时间 : 星期日 文章基于FPGA的数字频率计设计毕业设计更新完毕开始阅读311ca4a1dbef5ef7ba0d4a7302768e9950e76e73
目录
摘要 ......................................................................................................................................... III Abstract.................................................................................................................................... IV
第一章 绪论 ........................................................................................................................... III
1.1 课题的研究背景 ....................................................................................................... 1 1.2 频率计的发展现状 ................................................................................................... 1 1.3 课题研究的主要内容 ............................................................................................... 2 1.4 论文各章主要内容 ................................................................................................... 3 第二章 频率计测量原理 ......................................................................................................... 4
2.1 常用频率测量方法 ................................................................................................... 4
2.1.1 直读法测频 ................................................................................................... 4 2.1.2 比较法测频 ................................................................................................... 5 2.1.3 脉冲计数法测频 ........................................................................................... 5 2.2 脉冲计数法测量原理 ............................................................................................... 5 2.3 基于脉冲计数的直接测频法 ................................................................................... 6
2.3.1直接测频法原理 ............................................................................................ 6 2.3.2直接测频法误差及测频范围分析 ................................................................ 7 2.4 基于脉冲计数的周期测频法 ................................................................................... 7
2.4.1 周期测频法原理 ........................................................................................... 7 2.4.2 周期测频法的误差分析 ............................................................................... 8 2.5 本章小结 ................................................................................................................... 8 第三章 基于FPGA频率计的设计方案 ................................................................................. 9
3.1 FPGA的结构与工作原理 ......................................................................................... 9
3.1.1 查找表的原理与结构 ................................................................................... 9 3.1.2 FPGA的数字逻辑实现原理 ...................................................................... 10 3.2 EDA技术与VHDL ................................................................................................. 11
3.2.1 VHDL语言 .................................................................................................. 11
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3.2.2 EDA设计方法 ............................................................................................. 12 3.2.3 基于EDA工具的FPGA设计流程 ........................................................... 13 3.3 频率计的总体设计方案 ......................................................................................... 15 3.4 频率计各功能模块的设计原理 ............................................................................. 16
3.4.1 计数单元设计 ............................................................................................. 16 3.4.2 数码管拆分过程 ......................................................................................... 18 3.4.3 除法器设计 ................................................................................................. 19 3.5 本章小结 ................................................................................................................. 20 第四章 频率计各功能模块的设计实现 ............................................................................... 21
4.1 频率测量及显示控制模块 ..................................................................................... 21
4.1.1 测频闸门信号产生模块的设计 ................................................................. 21 4.1.2 测频闸门信号模块的端口信号 ................................................................. 21 4.1.3 测频闸门信号模块的VHDL设计流程 .................................................... 22 4.2 计数器模块 ............................................................................................................. 23
4.2.1 计数器的端口信号 ..................................................................................... 24 4.2.2 计数器的VHDL设计流程 ........................................................................ 24 4.3 除法器模块 ............................................................................................................. 25
4.3.1 除法器的端口信号 ..................................................................................... 25 4.3.2 除法器的设计原理 ..................................................................................... 26 4.3.3 除法器的VHDL实现 ................................................................................ 27 4.4 信号整形模块 ......................................................................................................... 28 4.5 电源模块 ................................................................................................................. 30 4.6 显示模块 ................................................................................................................. 31 4.7 数字频率计仿真 ..................................................................................................... 32
4.7.1 搭建硬件仿真平台 ..................................................................................... 32 4.7.2 除法器的仿真 ............................................................................................. 33 4.7.3 计数仲裁单元仿真 ..................................................................................... 33 4.7.4 计时过程仿真 ............................................................................................. 34 4.7.5 计数过程仿真 ............................................................................................. 34
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4.8 本章小结 ................................................................................................................. 35 结论 ......................................................................................................................................... 36 参考文献 ................................................................................................................................. 37 致谢 ......................................................................................................................................... 38
摘要
EDA技术的发展，改变了传统的电子设计方法。FPGA等大规模可编程逻辑器件的广泛应用，使电子设计变得和软件编程一样方便快捷。电子设计技术的进步，也改变了传统频率计的设计方法。
常用的频率测量方法既有模拟的利用电路频率特性测量频率的方法，又有利用脉冲计数测量频率的数字方法。随着数字电路技术的发展，以脉冲计数法为基础衍生出各种改进型的数字测频方法，在测量精度、测量响应的快速性等方面都有了很大提高。
本文分析了直接测频法和周期测频法的测量原理，说明了这两种测频方法产生±1 个计数误差的原因。多周期同步测频法由于实现了测频的闸门信号与被测脉冲信号的同步，消除了被测信号的±1个计数误差。文中对多周期同步测频原理进行了深入分析，并通过计算这三种测频方法的测量误差，说明了这三种测频方法的优缺点和适用的测频场合。由于多周期同步测频法的测量精度和被测信号的频率无关，是一种等精度测量方法，适用于宽范围的频率测量，所以本文采用多周期同步测频法来进行频率计的设计，给出了设计总体方案。最终设计了一种基于FPGA技术的数字频率计，应用VHDL硬件开发语言，在QuartusII集成开发环境进行了仿真实现。
关键词
数字频率计；直接测频法；FPGA；硬件开发语言
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Abstract
Development of EDA technology has changed the traditional method of electrical design. Extensive application of programmable logic devices such as FPGA has made the electrical design as convenient as software programming. The progress of electrical design technology also changed the traditional design method of frequency meter.
The common measurement method of frequency is to utilize the frequency characteristics of the circuit to measure frequency, and also to adopt numerical method of utilizing pulse counting to measure frequency. With the development of digital circuit technology, a variety of improved frequency measurement methods are produced based on pulse counting method. This paper analyzes the direct frequency measurement method and the measuring principle of periodic frequency measurement method, which shows the reasons why these two methods produce error of ± 1 counts. Multi-period synchronous frequency measurement method realized the synchronization of gate signal of frequency measurement and the measured pulse signal, eliminating the measured signal error of ± 1 counts. The paper analyzes the multi-period synchronous frequency measurement principle in depth and indicates the advantages and disadvantages of these three measurement methods and suitable measuring occasions by calculating the measurement error of these three methods. As the measurement accuracy of multi-period synchronous frequency measurement method is independent on the measured signal frequency, which is an equal-accquracy measurement method, it is applicable to a wide range of frequency measurement. The final design of the digital frequency meter, application development language VHDL hardware based on FPGA technology in QuartusII integrated development environment simulation implementation.
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