发布时间 : 星期六 文章eda数字钟设计程序更新完毕开始阅读34a8d8df7f1922791688e8bf
范明轲 0958200102 南京理工大学 2012 – 03 – 26
目 录
摘要及关键字······························································2 ABSTRACT··································································2 一. 设计要求·······························································2 二. 总体方案设计···························································3 三.各子模块设计原理······················································· 3 1.计秒模块······························································4 2.计分模块······························································5 3.计时模块······························································6 4.计周模块······························································8 5.计日模块······························································9 6.计月模块·····························································14 7.计年模块·····························································16 8.校准模块·····························································18 9. 闹钟模块····························································20 10.选择模块····························································21 11.显示模块·····························································22 12.报时模块·····························································24 13.分频模块·····························································25 14.去抖动模块···························································27 四. 硬件下载与测试························································16 1.硬件下载······························································16 2.测试··································································17 3.功能扩展······························································17 五.结论···································································17 参考文献··································································18
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范明轲 0958200102 南京理工大学 2012 – 03 – 26
数字电子钟的设计
摘要及关键字：
数字电子钟是生活中最常用的电子设备之一，其主要功能是能够显示时、分、秒实时信息，并能够方便地进行年，月，周，日，时、分、秒的初始值设置，以便时间校准。
实现数字电子钟有很多方法，本课程是采用VHDL硬件语言的强大描述能力和EDA工具的结合在电子设计领域来设计一个具有多功能的数字电子钟。
关键字： 数字电子钟
ABSTRACT:
VHDL硬件语言 EDA工具
Digital electric clock in life are the most commonly used one of the electronic equipment. Its main function is to display, minutes and seconds real-time information and can be easily when carried out, minutes and seconds, so that the initial value is set time calibration.
There are many methods of design digital electric clock.This course is a powerful by VHDL hardware language describe ability and EDA tools in electronic design field with versatile to design a digital electric clock .
Key work: Digital electric clock
一． 设计要求:
VHDL hardware language EDA tools
1. 设计一个电子钟能够显示年（能计瑞年），月，周，日，时，分，秒；24小时循环显示。
2. 电子钟有校时，校分，清零，保持，整点报时和闹钟的功能，具体如下： （1） 数字钟最大计时显示99年12月31日23点59分59秒 。
（2） 在数字钟正常工作时可以对数字钟进行快速校日、校分，即拨动开关K5
可以对日进行校正，拨动开关K1可以对分进行校正。
（3） 在数字中正常工作情况下可以对其进行不断地复位，即拨动开关K3可以
是时，分，秒显示回零。
（4） 在数字钟正常工作时拨动开关K2可以使数字钟保持原有显示，停止计
时。
（5） 整点报时是要求数字钟在每小时整点到来前进行鸣叫，鸣叫频率是在
59:53, 59:55, 59:57 为1kHz，59:59为2kHz。
（6） 当开关K7，K8（即等于11或10）就可以看到正常计数时钟界面，有
星期 ：小时：分钟：秒钟。
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范明轲 0958200102 南京理工大学 2012 – 03 – 26
当k7,k8(等于01) 是在输入定时闹钟界面，有小时：分钟 当 K7，K8 等于 00 是在 万年显示，有 年：月：日
3. 要求所有开关具有去抖动功能。利用开发工具Quartus II 7.0并结合硬件描述语言VHDL，采用层次化的方法进行设计，要求设计层次清晰，合理；构成整个设计的功能可以采用原理图输入或文本输入法实现。 4. 通过开发工具Quartus II 7.0对设计电路进行功能仿真。 5. 将仿真通过的逻辑电路下载到EDA试验系统，对其功能进行验证。
二． 总体方案设计:
从设计要求可以对其进行层次化设计，将所要设计的多功能数字钟分层6个模块：
(1) 计时模块: 包括两个模60的计数器(计秒与计分)和一个模24的计数器(计
时)。
(2) 清零，保持模块： 此模块功能是可以在计时模块直接嵌入即利用计数器的清
零、保持 功能就可以实现。 (3) 校准模块: 其对时、分进行校正。 (4) 显示模块: 将数字钟在数码管上显示。
(5) 整点报时模块: 由两部分组成，一部分选择报时时间(59:53, 59:55,
59:57,59:59)，一部分选择报时频率(1kHz，2kHz)。
(6) 分频模块: 电子钟的激励源要求的是稳定1Hz，而试验台提供48MHz的时钟，
所以要设计一个分频器将48MHz进行分频得到1Hz。
(7) 防抖动模块：因为设计中有使用到开关，而对机械开关而言出现抖动现象 会导致系统误差甚至不能正常工作。所以在设计中要求有去抖动电路。
将数字钟的各功能模块级联，生成顶层电路，实现总体设计要求，设计框图如下图所示：
清零
保持
显示 模块 计时 校时 模块
校分 报时，闹钟 模块 分频 模块 3
范明轲 0958200102 南京理工大学 2012 – 03 – 26
三． 各子模块设计原理:
1. 计秒模块: 是一个模60的计数器，具有计时、保持、清零的功能。采用VHDL硬件
语言编写，程序代码如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY second IS
PORT( clk: IN STD_LOGIC; rst: IN STD_LOGIC; en: IN STD_LOGIC;
qout1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); qout2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); co: OUT STD_LOGIC); END second;
ARCHITECTURE behav OF second IS
SIGNAL tem1: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL tem2: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
PROCESS(clk,rst) BEGIN
IF(en='1')THEN tem1<=tem1; tem2<=tem2; ELSIF(rst='0')THEN tem1<=\ tem2<=\
ELSIF(clk'event AND clk='1')THEN IF tem1=\ tem1<=\
IF tem2=\ tem2<=\ co<='1'; ELSE
tem2<=tem2+1; co<='0'; END IF; ELSE
tem1<=tem1+1; END IF; END IF;
qout1<=tem1; qout2<=tem2; END PROCESS; END behav;
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