发布时间 : 2024/6/14 9:48:58 星期五 文章基于VHDL的2FSK调制与解调更新完毕开始阅读36eb6ad649649b6648d74770

河北大学工商学院2012届本科生毕业论文(设计)

附 录

调制部分程序 libraryieee;

useieee.std_logic_arith.all; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityPPPL_FSKis port(clk:instd_logic; start:instd_logic; x:instd_logic; y:outstd_logic); endPPPL_FSK;

architecturebehavofPPPL_FSKis signalq1:integerrange0to15; signalq2:integerrange0to3; signalf1,f2:std_logic; begin process(clk) begin

ifclk'eventandclk='1'then ifstart='0'thenq1<=0;

elsifq1<=7thenf1<='1';q1<=q1+1;

elsifq1=15thenf1<='0';q1<=0; elsef1<='0';q1<=q1+1; endif endif; endprocess; process(clk) begin

ifclk'eventandclk='1'then ifstart='0'thenq2<=0;

elsifq2<=0thenf2<='1';q2<=q2+1; elsifq2=1thenf2<='0';q2<=0;

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河北大学工商学院2012届本科生毕业论文(设计)

elsef2<='0';q2<=q2+1; endif; endif; endprocess; process(clk,x) begin

ifclk'eventandclk='1'then ifx='0'theny<=f1; elsey<=f2; endif; endif; endprocess; endbehav;

解调部分程序

libraryieee;

useieee.std_logic_arith.all; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityDL_FSKis port(clk:instd_logic; start:instd_logic; x:instd_logic; y:outstd_logic); endDL_FSK;

architecturebehavofDL_FSKis signalq:integerrange0to15; signalxx:std_logic; signalm:integerrange0to5; begin process(clk) begin

ifclk'eventandclk='1'thenxx<=x; ifstart='0'thenq<=0; elsifq=15thenq<=0;

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河北大学工商学院2012届本科生毕业论文(设计)

elseq<=q+1; endif; endif; endprocess; process(xx,q) begin

ifq=15thenm<=0; elsifq=10then ifm<=3theny<='0'; elsey<='1'; endif;

elsifxx'eventandxx='1'thenm<=m+1; endif; endprocess; endbehav;

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