发布时间 : 星期六 文章基于VHDL的空调控制器设计更新完毕开始阅读435405e44793daef5ef7ba0d4a7302768f996f47
U1: switch PORT MAP(a=>switchin,b=>swb,c=>swa,clk=>clk1,d=>sigBCD7_1); U2: control PORT MAP(a=>switchin,b=>swc,clk=>clk1,c=>swb); U3: fan PORT MAP(a=>swa,b=>fanup,c=>fandown,clk=>clk1,di=>dis,zhong=>zhongs,gao=>gaos,ssleep=>sigBCD7_2,sdi=>sigBCD7_3,szhong=>sigBCD7_4,sgao=>sigBCD7_5); U4: temp PORT MAP(a=>swa,b=>tempup,c=>tempdown,clk=>clk1,temp1=>sigBCD7_6,temp2=>sigBCD7_7); U5: timer PORT MAP(a=>swa,clk1=>clk1,clk2=>clk2,b=>timerop,c=>timercancel,up=>timerup,down=>timerdown,sw1=>swc,oh1=>sigBCD7_8,oh2=>sigBCD7_9,ot1=>sigBCD7_10,ot2=>sigBCD7_11); U6: mode PORT MAP(b=>swa,c=>modeset,clk=>clk1,cool=>cools,heat=>heats,dry=>drys,cool1=>sigBCD7_12,heat1=>sigBCD7_13,dry1=>sigBCD7_14);
U7: BCD7 PORT MAP(a=>swa,b=>sigBCD7_1,q=>switchstate); U8: BCD7 PORT MAP(a=>swa,b=>sigBCD7_2,q=>sleepstate); U9: BCD7 PORT MAP(a=>swa,b=>sigBCD7_3,q=>distate);
U10: BCD7 PORT MAP(a=>swa,b=>sigBCD7_4,q=>zhongstate); U11: BCD7 PORT MAP(a=>swa,b=>sigBCD7_5,q=>gaostate); U12: BCD7 PORT MAP(a=>swa,b=>sigBCD7_6,q=>tempd); U13: BCD7 PORT MAP(a=>swa,b=>sigBCD7_7,q=>temps); U14: BCD7 PORT MAP(a=>swa,b=>sigBCD7_8,q=>hdstate); U15: BCD7 PORT MAP(a=>swa,b=>sigBCD7_9,q=>hsstate); U16: BCD7 PORT MAP(a=>swa,b=>sigBCD7_10,q=>tdstate); U17: BCD7 PORT MAP(a=>swa,b=>sigBCD7_11,q=>tsstate); U18: BCD7 PORT MAP(a=>swa,b=>sigBCD7_12,q=>coolstate); U19: BCD7 PORT MAP(a=>swa,b=>sigBCD7_13,q=>heatstate); U20: BCD7 PORT MAP(a=>swa,b=>sigBCD7_14,q=>drystate); PROCESS(clk1) BEGIN
END PROCESS;
END ARCHITECTURE behave;
2）单脉冲模块
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY pulse IS --单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END ENTITY pulse;
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ARCHITECTURE behave OF pulse IS SIGNAL d:STD_LOGIC:='0'; SIGNAL f:STD_LOGIC:='0';
SIGNAL g:STD_LOGIC:='0'; --确保经过第一个clk上升沿时输出1 SIGNAL h:STD_LOGIC:='0'; --同上 BEGIN
PROCESS(a,clk) BEGIN
IF(clk'EVENT AND clk='1')THEN IF(f='1')THEN g<='1';
ELSE g<='0'; END IF; END IF;
END PROCESS; PROCESS(a,clk) BEGIN
IF(clk'EVENT AND clk='0')THEN IF(a='1')THEN IF(f='1')THEN IF(g='1')THEN d<='1'; ELSE d<='0'; END IF; ELSE d<='1'; END IF;
ELSE d<='0'; --a为0时，重置此单脉冲发生器 END IF; END IF;
END PROCESS; PROCESS(d) BEGIN IF(a='1')THEN IF(d='1')THEN f<='0';
ELSE f<='1'; END IF; ELSE f<='0'; END IF; b<=f;
END PROCESS;
END ARCHITECTURE behave;
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3）开关模块
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY switch IS --开关模块
PORT(a,b,clk: IN STD_LOGIC; --b受定时模块的控制，时间减为0时，关闭开关
c: OUT STD_LOGIC;
d: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); --输送给数码管 END ENTITY switch;
ARCHITECTURE behave OF switch IS
COMPONENT pulse --调用单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL p1 : STD_LOGIC:='0'; SIGNAL p2 : STD_LOGIC:='0'; BEGIN
U1: pulse PORT MAP(a=>a,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>b,b=>p2,clk=>clk); PROCESS(a,b,clk) BEGIN
IF(clk'EVENT AND clk='1')THEN IF(p1='1')THEN --空调开关打开 c<='1';d<=\ END IF;
IF(p2='1')THEN --时间减为0时，定时模块返回1，关闭开关 c<='0';d<=\ END IF; END IF; END PROCESS;
END ARCHITECTURE behave;
4）开关控制模块
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY control IS --开关控制模块 PORT(a,b,clk: IN STD_LOGIC; c: OUT STD_LOGIC); END ENTITY control;
ARCHITECTURE behave OF control IS
COMPONENT pulse --调用单脉冲模块
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PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse; SIGNAL p1 : STD_LOGIC:='0'; SIGNAL p2 : STD_LOGIC:='0'; BEGIN
U1: pulse PORT MAP(a=>a,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>b,b=>p2,clk=>clk); PROCESS(a,b,clk) BEGIN
IF(clk'EVENT AND clk='1')THEN IF(p1='1')THEN --空调开关打开 c<='0'; END IF;
IF(p2='1')THEN --时间减为0时，定时模块返回1，关闭开关 c<='1'; END IF; END IF; END PROCESS;
END ARCHITECTURE behave;
5）温度模块
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
ENTITY temp IS --温度模块,最高30度，最低16度，默认26度 PORT(a,b,c,clk: IN STD_LOGIC; --a控制开关，b提高1度，c降低1度 temp1,temp2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY temp;
ARCHITECTURE behave OF temp IS
COMPONENT pulse --调用单脉冲模块 PORT(a,clk: IN STD_LOGIC; b: OUT STD_LOGIC); END COMPONENT pulse;
SIGNAL t1 : STD_LOGIC_VECTOR(3 DOWNTO 0):=\SIGNAL t2 : STD_LOGIC_VECTOR(3 DOWNTO 0):=\SIGNAL p1 : STD_LOGIC:='0'; SIGNAL p2 : STD_LOGIC:='0'; SIGNAL p3 : STD_LOGIC:='0'; BEGIN
U1: pulse PORT MAP(a=>b,b=>p1,clk=>clk); U2: pulse PORT MAP(a=>c,b=>p2,clk=>clk);
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