发布时间 : 2024/7/19 13:47:08 星期五 文章华中科技大学数字逻辑实验小设计更新完毕开始阅读53ad5536e109581b6bd97f19227916888586b996

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module JDYS_tb( );

reg CIN,S1,S0,CP; reg [3:0] A; reg [3:0] B; reg [3:0] C; reg [3:0] D; wire [3:0] F;

JDYS DUT (.A(A), .B(B), .C(C), .D(D), .S1(S1), .S0(S0), .CP(CP), .CIN(CIN), .F(F)); initial begin

A = 4'd12;B = 4'd11;C = 4'd2;D = 4'd8;S1 = 0;S0 = 0;CIN = 0;CP = 1; #10

S1 = 0; S0 = 1; CIN = 1; CP = 0;

#10

S1 = 1; S0 = 0;

#10

S1 = 1; S0 = 1;

#10

A = 4'd5; B = 4'd7; C = 4'd5; D = 4'd1; S1 = 0; S0 = 0; CIN = 0; CP = 1;

#10

S1 = 0; S0 = 1; CIN = 1; CP = 0;

#10

S1 = 1; S0 = 0;

#10

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S1 = 1; S0 = 1;

#10

A = 4'd0; B = 4'd15; C = 4'd4; D = 4'd8; S1 = 0; S0 = 0; CIN = 0; CP = 1;

#10

S1 = 0; S0 = 1; CIN = 1; CP = 0;

#10

S1 = 1; S0 = 0;

#10

S1 = 1;

S0 = 1;

#10; end

endmodule

运算电路电路图：

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运算电路仿真波形图：

参考文献：

[1]欧阳星明、于俊清等.《数字逻辑》（第四版）华中科技大学出版社，.hustp．

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