发布时间 : 2024/6/9 12:18:31 星期日 文章飞思卡尔XS128系列pll锁相环更新完毕开始阅读546ef42ecfc789eb172dc876

CLKSEL=0X00; //disengage PLL to system PLLCTL_PLLON=1; //turn on PLL SYNR =0xc0 | 0x0b; REFDV=0x80 | 0x01;

POSTDIV=0x00; //pllclock=2*osc*(1+SYNR)/(1+REFDV)=192MHz; _asm(nop); //BUS CLOCK=96M _asm(nop);

while(!(CRGFLG_LOCK==1)); //when pll is steady ,then use it; CLKSEL_PLLSEL =1; //engage PLL to system; }

void SetBusCLK_104M(void) {

CLKSEL=0X00; //disengage PLL to system PLLCTL_PLLON=1; //turn on PLL SYNR =0xc0 | 0x0c; REFDV=0x80 | 0x01;

POSTDIV=0x00; //pllclock=2*osc*(1+SYNR)/(1+REFDV)=208MHz; _asm(nop); //BUS CLOCK=104M _asm(nop);

while(!(CRGFLG_LOCK==1)); //when pll is steady ,then use it; CLKSEL_PLLSEL =1; //engage PLL to system; }

void SetBusCLK_120M(void) {

CLKSEL=0X00; //disengage PLL to system PLLCTL_PLLON=1; //turn on PLL SYNR =0xc0 | 0x0d; REFDV=0x80 | 0x01;

POSTDIV=0x00; //pllclock=2*osc*(1+SYNR)/(1+REFDV)=240MHz; _asm(nop); //BUS CLOCK=120M _asm(nop);

while(!(CRGFLG_LOCK==1)); //when pll is steady ,then use it; CLKSEL_PLLSEL =1; //engage PLL to system; }