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TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_Low ;//High; /*AOE=1*/ TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable; //×Ô¶¯Êä³öʹÄÜ TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure); //TIM2->BDTR |=1<<14; //AOE???1 TIM_SelectInputTrigger(TIM1, TIM_TS_ITR1); // TIM1->SMCR |=0x0010; /*trigger interrupt enable*/ TIM1->DIER |=0x0040;//set TIE TIM_Cmd(TIM1,ENABLE); //TIM1->CR1 |= 0x0001;

TIM_CtrlPWMOutputs(TIM1, ENABLE);//MOEλÖÃ1 //TIM1->BDTR|=1<<15; }

// Æô¶¯TIM1ºÍTIM2¶¨Ê±Æ÷ void start(void) { /*Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled*/ TIM1->SMCR |=0x0016; //¿ªTIM1¼ÆÊýÆ÷´¥·¢ /*Trigger interrupt enabled*/ TIM1->DIER |=0x0040; //¿ªTIM1´¥·¢ÖÐ¶Ï // huan_xiang(); // /*Counter enable*/ TIM2->CR1|=0x0001; //¿ªTIM2 /*Trigger and Update interrupt enabled*/ TIM2->DIER|=0x0041; //¿ªTIM2ÖÐ¶Ï }

void huan_xiang() { step = GPIO_ReadInputData(GPIOA)&0x0007; if(direction_flag==MotorForwardFlag) { switch(step)//¸ù¾Ýת×ÓλÖ㬾ö¶¨CCERÊä³öÏàλºÍת×ÓÆ«ÒÆÁ¿ { case 0x06: { /*0011 0100 0010 0000 reset CC3NP CC3P CC3E CC2NP CC2NE CC2E CC1NP CC1NE CC1P CC1E set CC2P OC2 active low,set CC3NE OC3N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS3, OIS3N and CC3E bits set CC4P OC4 active low,set CC4E OC4 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1->CCER =0x3420;// };

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break; case 0x04: { /*0011 0000 0010 0100 set CC2P OC2 active low,set CC1NE OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1->CCER =0x3024;// }; break; case 0x05: { /*0011 0010 0000 0100 set CC3P OC3 active low,set CC1NE OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1->CCER =0x3204;// }; break; case 0x01: { /*0011 0010 0100 0000 set CC3P OC3 active low,set CC2NE OC2N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS2, OIS2N and CC2E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1->CCER =0x3240;// }; break; case 0x03: { /*0011 0000 0100 0010 set CC1P OC3 active low,set CC2NE OC2N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS2, OIS2N and CC2E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1->CCER =0x3042;// };

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break; case 0x02: { /*0011 0100 0000 0010 set CC1P OC1 active low,set CC3NE OC3N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS3, OIS3N and CC3E bits set CC4P OC4 active low,set CC4E OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS4, OIS4N and CC4NE bits */ TIM1->CCER =0x3402;// }; break; } } else//µ¹×ª { switch(step) { // case 0x06: { TIM1->CCER =0x3420; // 3?2 }; break; case 0x04: { TIM1->CCER =0x3024; // 3?6 }; break; case 0x05: { TIM1->CCER =0x3204; // 1?6 }; break; case 0x01: { TIM1->CCER =0x3240; // 1?4 }; break; case 0x03: { TIM1->CCER =0x3042; };

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break; case 0x02: { TIM1->CCER =0x3402; }; break; default: { TIM1->CCER =0x0000; } break; } } }

//¶¨Ê±Æ÷2²É¼¯»ô¶ûÐźţ¬²úÉúÁù²½»»ÏòµÄ´¥·¢ÖжÏÌõ¼þ void TIM2_Configuration(void) { TIM_TimeBaseInitTypeDef TIM_HALLTimeBaseInitStructure; TIM_ICInitTypeDef TIM_HALLICInitStructure; TIM_OCInitTypeDef TIM_HALLOCInitStructure; /*Deinitializes the TIM2 peripheral registers to their default reset values */ TIM_DeInit(TIM2); /*Fills each TIM_TimeBaseInitStruct member with its default value Set the default configuration TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; */ TIM_TimeBaseStructInit(&TIM_HALLTimeBaseInitStructure); // Set full 16-bit working range TIM_HALLTimeBaseInitStructure.TIM_Period = 65535;//TIM2_ARR=65535 //PSCÔ¤·ÖƵ ¼ÆÊýÆ÷µÄʱÖÓƵÂÊCK_CNT=fck_psc/(psc[15:0]+1) 1MHz TIM_HALLTimeBaseInitStructure.TIM_Prescaler = 71;//1us¼ÆÊý1 TIM_HALLTimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;//CR1 ÏòÉϼÆÊý TIM_HALLTimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;//CR1 ¶¨Ê±Æ÷ʱÖÓƵÂʺÍÊý×ÖÂ˲¨Æ÷ʹÓõIJÉÑùƵÂÊÖ®¼äµÄ·ÖƵ±ÈÀý /*ÿ´Î´ÓÁ㿪ʼ¼ÆÊýʱ£¬²úÉú¸üÐÂʼþ£¨UEV£©*/ TIM_HALLTimeBaseInitStructure.TIM_RepetitionCounter = 0;//RCR TIM_TimeBaseInit(TIM2,&TIM_HALLTimeBaseInitStructure); /*Fills each TIM_ICInitStruct member with its default value Set the default configuration

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