发布时间 : 星期三 文章《EDA技术实用教程第四版》习题答案.更新完毕开始阅读84ae4f70657d27284b73f242336c1eb91a37332c
ELSE Q<=(OTHERS=>'0'); --大于等于9时，计数值清零 END IF; END IF; END IF; END IF; END IF; END PROCESS; COM: PROCESS(Q) BEGIN
IF Q=12 THEN COUT<='1'; --计数大于9，输出进位信号 ELSE COUT<='0'; END IF;
DOUT<=Q; --将计数值向端口输出 END PROCESS; END behav;
3-5 设计含有异步清零和计数使能的16位二进制加减可控计数器。
--解：用VHDL实现含有异步清零和计数使能的16位二进制加减可控计数器。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADD_SUB_16 IS
PORT (CLK,RST,ADD_EN,SUB_EN: IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; COUT: OUT STD_LOGIC); END ENTITY ADD_SUB_16;
ARCHITECTURE A_S_16 OF ADD_SUB_16 IS BEGIN
PROCESS(CLK,RST,ADD_EN,SUB_EN)
VARIABLE CQI: STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN
IF RST = '1' THEN CQI:=(OTHERS => '0');--计数器异步复位 ELSIF CLK'EVENT AND CLK='1' THEN --检测时钟上升沿 IF ADD_EN='1'THEN --检测是否允许计数(同步他能)
IF CQI<16#FFFF# THEN CQI:=CQI+1; --允许计数,检测是否小于65535 ELSE CQI:=(OTHERS => '0'); --大于65535,计数值清零 END IF;
IF CQI=16#FFFF# THEN COUT<='1'; --计数大于9,输出进位信号 ELSE COUT <= '0'; END IF; END IF;
IF SUB_EN='1'THEN --检测是否允许计数(同步他能)
IF CQI>0 THEN CQI:=CQI-1; --允许计数,检测是否小于65535 ELSE CQI:=(OTHERS => '1'); --大于65535,计数值清零 END IF;
IF CQI=0 THEN COUT<='1'; --计数大于9,输出进位信号 ELSE COUT <= '0'; END IF; END IF; END IF;
CQ<=CQI; --将计数值向端口输出 END PROCESS;
END ARCHITECTURE A_S_16;
3-6 图3-18是一个含有上升沿触发的D触发器的时序电路(sxdl),试写出此电路的VHDL设计文件。
图3-18 时序电路
--解：实现图4-19电路的VHDL程序t4_19.vhd LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY t4_19 IS
PORT (CL,CLK0: IN STD_LOGIC; OUT1: OUT STD_LOGIC); END ENTITY t4_19;
ARCHITECTURE sxdl OF t4_19 IS ----时序电路sxdl SIGNAL Q : STD_LOGIC; BEGIN
PROCESS(CLK0) BEGIN
IF CLK0'EVENT AND CLK0='1' THEN --检测时钟上升沿 Q <= NOT(Q OR CL); END IF;
END PROCESS; OUT1 <= NOT Q;
END ARCHITECTURE sxdl;
3-7 给出1位全减器的VHDL描述；最终实现8位全减器。要求:
1)首先设计1位半减器,然后用例化语句将它们连接起来,图4-20中h_suber是半减器,diff是
a xin 输出差(diff=x-y),s_out是借位输出(s_out=1,x diff_out c yin b 图3-19 1位全加器 --解(1.1)：实现1位半减器h_suber(diff=x-y；s_out=1,x PORT( x,y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END ENTITY h_suber; ARCHITECTURE hs1 OF h_suber IS BEGIN Diff <= x XOR (NOT y); s_out <= (NOT x) AND y; END ARCHITECTURE hs1; --解(1.2)：采用例化实现图4-20的1位全减器 LIBRARY IEEE; --1位二进制全减器顺层设计描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_suber IS PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END ENTITY f_suber; ARCHITECTURE fs1 OF f_suber IS COMPONENT h_suber --调用半减器声明语句 PORT(x, y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END COMPONENT; SIGNAL a,b,c: STD_LOGIC; --定义1个信号作为内部的连接线。 BEGIN u1: h_suber PORT MAP(x=>xin,y=>yin, diff=>a, s_out=>b); u2: h_suber PORT MAP(x=>a, y=>sub_in, diff=>diff_out,s_out=>c); sub_out <= c OR b; END ARCHITECTURE fs1; (2)以1位全减器为基本硬件,构成串行借位的8位减法器,要求用例化语句来完成此项设计(减法运算是x-y-sun_in=difft)。 x7 y7 a6 x1 y1 xin sub_out yin u7 sub_in diff_out ………………. ………………. xin sub_out yin u1 sub_in diff_out xin sub_out yin u0 sub_in diff_out 串行借位的8位减法器 a1 sout diff7 a0 diff1 diff0 x0 y0 sin --解(2)：采用例化方法，以1位全减器为基本硬件；实现串行借位的8位减法器(上图所示)。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY suber_8 IS PORT(x0,x1,x2,x3,x4,x5,x6,x7: IN STD_LOGIC; y0,y1,y2,y3,y4,y5,y6,y7,sin: IN STD_LOGIC; diff0,diff1,diff2,diff3: OUT STD_LOGIC; diff4,diff5,diff6,diff7,sout: OUT STD_LOGIC); END ENTITY suber_8; ARCHITECTURE s8 OF suber_8 IS COMPONENT f_suber --调用全减器声明语句 PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END COMPONENT; SIGNAL a0,a1,a2,a3,a4,a5,a6: STD_LOGIC; --定义1个信号作为内部的连接线。 BEGIN u0:f_suber PORT MAP(xin=>x0,yin=>y0,diff_out=>diff0,sub_in=>sin,sub_out=>a0); u1:f_suber PORT MAP(xin=>x1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1); u2:f_suber PORT MAP(xin=>x2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2); u3:f_suber PORT MAP(xin=>x3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3); u4:f_suber PORT MAP(xin=>x4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4); u5:f_suber PORT MAP(xin=>x5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5); u6:f_suber PORT MAP(xin=>x6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6); u7:f_suber PORT MAP(xin=>x7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout); END ARCHITECTURE s8; 3-8 给出一个4选1多路选择器的VHDL描述。选通控制端有四个输入：S0、S1、S2、S3。当且仅当S0=0时:Y=A；S1=0时:Y=B；S2=0时:Y=C；S3=0时:Y=D。 --解：4选1多路选择器VHDL程序设计。 LIBRARY IEEE; --图3-20(c)RTL图的VHDL程序顶层设计描述