发布时间 : 星期六 文章基于VHDL的数字闹钟设计 - 图文更新完毕开始阅读878bc054ad02de80d4d840c0
第四章 模块电路设计
end process m110;
----------------------------------------------分钟个位 m220:process(clk,sec1,sec2,md1,md2) begin
if clk'event and clk='1' then
if min2=\min2<=\
elsif min2=\min2<=\
else if (sec1=\min2<=min2+1; end if;
end if;end if;
end process m220;
---------------------------------------------秒十位 s110:process(clk) begin
if clk'event and clk='1' then
if (sec1=\sec1<=\
else if sec2=\sec1<=sec1+1; end if;
end if;end if; end process s110;
--------------------------------------------秒个位 s220:process(clk) begin
if clk'event and clk='1' then if sec2=\sec2<=\else sec2<=sec2+1; end if; end if;
end process s220;
-------------------------------------------时间设置小时部分 sethour1:process(clk,seth2) begin
if clk'event and clk='1' then
if seth1=\seth1<=\
elsif seth2=\ then seth1<=seth1+1; end if; end if;
end process sethour1;
sethour2:process(clk,md1,md2,seth1) begin
if clk'event and clk='1' then
if (seth1=\
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选题背景
seth2<=\
elsif md1='1' and md2=\seth2<=seth2+1; end if; end if;
end process sethour2;
-------------------------------------------时间设置分钟部分 setmin1:process(clk,setm2) begin
if clk'event and clk='1' then
if setm1=\setm1<=\
elsif setm2=\setm1<=setm1+1; end if; end if;
end process setmin1;
setmin2:process(clk,md1,md2) begin
if clk'event and clk='1'then if setm2=\setm2<=\
elsif md1='1' and md2=\setm2<=setm2+1; end if; end if;
end process setmin2;
--------------------------------------------闹铃 speaker:process(clk,hou1,hou2,min1,min2) begin
if clk'event and clk='1'then
if seth1=hou1 and seth2=hou2 and setm1=min1 and setm2=min2 then clken<='1'; else clken<='0'; end if; end if;
end process speaker;
disp:process(md1,hou1,hou2,min1,min2,sec1,sec2,seth1,seth2,setm1,setm2) begin
if md1='0' then---------------计时时间显示和设置模式 h1<=hou1;h2<=hou2; m1<=min1;m2<=min2; s1<=sec1;s2<=sec2;
else -----------闹铃时间现实和设置模式 h1<=seth1;h2<=seth2; m1<=setm1;m2<=setm2; s1<=\end if;
end process disp; end one;
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第四章 模块电路设计
3）乐曲演奏模块： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Speakera IS
PORT ( clk : IN STD_LOGIC;
Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END;
ARCHITECTURE one OF Speakera IS
SIGNAL PreCLK, FullSpkS : STD_LOGIC; BEGIN
DivideCLK : PROCESS(clk)
VARIABLE Count4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN
PreCLK <= '0'; -- 将CLK进行16分频，PreCLK为CLK的16分频 IF Count4>11 THEN PreCLK <= '1'; Count4 := \
ELSIF clk'EVENT AND clk = '1' THEN Count4 := Count4 + 1; END IF; END PROCESS;
GenSpkS : PROCESS(PreCLK, Tone)-- 11位可预置计数器
VARIABLE Count11 : STD_LOGIC_VECTOR (10 DOWNTO 0); BEGIN
IF PreCLK'EVENT AND PreCLK = '1' THEN
IF Count11 = 16#7FF# THEN Count11 := Tone ; FullSpkS <= '1'; ELSE Count11 := Count11 + 1; FullSpkS <= '0'; END IF; END IF; END PROCESS;
DelaySpkS : PROCESS(FullSpkS)--将输出再2分频，展宽脉冲，使扬声器有足够功率发音
VARIABLE Count2 : STD_LOGIC; BEGIN
IF FullSpkS'EVENT AND FullSpkS = '1' THEN Count2 := NOT Count2; IF Count2 = '1' THEN SpkS <= '1'; ELSE SpkS <= '0'; END IF;
END IF; END PROCESS; END;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY NoteTabs IS
PORT (clk : IN STD_LOGIC;
ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END;
ARCHITECTURE one OF NoteTabs IS
COMPONENT MUSIC --音符数据ROM PORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
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选题背景
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END COMPONENT;
SIGNAL Counter : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN
CNT8 : PROCESS(clk,Counter) BEGIN
IF Counter=138 THEN Counter <= \
ELSIF (clk'EVENT AND clk = '1') THEN Counter <= Counter+1; END IF; END PROCESS;
u1 : MUSIC PORT MAP(address=>Counter , q=>ToneIndex, inclock=>clk); END;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY ToneTaba IS
PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); en : IN STD_LOGIC); END;
ARCHITECTURE one OF ToneTaba IS BEGIN
PROCESS(Index,en) BEGIN
IF en='0' THEN Tone<=\使能信号 ELSE
CASE Index IS -- 译码电路，查表方式，控制音调的预置数 WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => NULL; END CASE; END IF;
END PROCESS; END;
LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all; ENTITY music IS PORT
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