海思方案 HI3518E平台ISP调试环境搭建 联系客服

发布时间 : 星期日 文章海思方案 HI3518E平台ISP调试环境搭建更新完毕开始阅读884c5e37905f804d2b160b4e767f5acfa1c783fc

3518E平台的搭建

海思的SDK提供了ISP调试的相关工具,降低了IPC开发ISP调试的难度。初次搭建ISP调试环境,记录一下。 SDK版本:Hi3518_MPP_V1.0.A.0 硬件平台:HI3518E_OV9732

工具包:PQ_TOOL (Hi3518E_V100R001C01SPC0A0\\01.software\\pc\\PQ_TOOL)

文件说明:Hi3518_ITTB_MPP2_V1.0.A.0_B030.tgz 设备端工具 ; PQTools_V3.7.5.zip PC端工具 环境搭建步骤:

(1)将Hi3518_ITTB_MPP2_V1.0.A.0_B030.tgz拷贝至nfs共享目录名,解压后运行HiIspTool.sh脚本 倘若用海思自带的工具出图像并调节ISP运行:

#./HiIspTool.sh -a -p ov9732_720p_line.ini ps一下可以看到两个进程

696 adminlvj 58488 S ./ittb_stream -p ov9732_720p_line.ini 699 adminlvj 19676 S ./ittb_control

倘若运行自己的工程出图像了,这时只需要运行一下命令即可。 #./HiIspTool.sh -a ps一下可以看到一个进程

699 adminlvj 19676 S ./ittb_control

(2)PC端直接解压PQTools_V3.7.5.zip,运行HiPQTools.exe,输入选择sdk版本Hi3518_MPP_V1.0.A.0 ,输入设备IP,就可以连接上摄像头

倘若运行了ittb_stream,可以PC端软件上打开视频图像窗口

连接成功,至此,最简单的ISP调试环境搭建就完成了。复杂的就是后面的ISP调节过程了。

备注:

运行脚本的时候可能会报错,查看相关打印信息,将错误消除。当前产品我们用的是HI3518E+OV9732,SDK中并没有提供相关的sensor库和相关的config文件,所以运行报错了!

解决:将OV9732sensor库拷贝至Hi3518_ITTB_MPP2_V1.0.A.0/libs/下,将ov9732_720p_line.ini拷贝至Hi3518_ITTB_MPP2_V1.0.A.0/configs/下

附录:

ov9732_720p_line.ini

[plain] view plaincopyprint?

1. 2. 3. 4. 5.

[sensor]

Sensor_type =ov9732 ;the type of sensor

Mode =0 ;LINE mode,mode = 0 ,WDR mode,mode =1 DllFile =libs/libsns_ov9732.so ;LineDllFile path

6. [vi_dev]

7. Input_mod =2 ;VI_INPUT_MODE_BT656 = 0 8. ;VI_INPUT_MODE_BT601,

9. ;VI_INPUT_MODE_DIGITAL_CAMERA 10.

11. Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0 12.

13. ;VI_WORK_MODE_2Multiplex, 14.

15. ;VI_WORK_MODE_4Multiplex 16.

17. Combine_mode =0 ;Y/C composite or separation mode 18.

19. ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */ 20.

21. ;VI_COMBINE_SEPARATE, /*Separate mode */ 22.

23. Comp_mode =0 ;Component mode (single-component or dual-component) 24.

25. ;VI_COMP_MODE_SINGLE = 0, /*single component mode */ 26.

27. ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */ 28.

29. Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge) 30.

31. ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ 32.

33. ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ 34.

35. Mask_num =2 ;Component mask 36.

37. Mask_0 =0xFFC00000 38.

39. Mask_1 =0x0 40.

41. Scan_mode = 1;VI_SCAN_INTERLACED = 0 42.

43. ;VI_SCAN_PROGRESSIVE, 44.

45. Data_seq =2 ;data sequence (ONLY for YUV format) 46.

47. ;----2th component U/V sequence in bt1120 48.

49. ; VI_INPUT_DATA_VUVU = 0, 50.

51. ; VI_INPUT_DATA_UVUV, 52.

53. ;----input sequence for yuv 54.

55. ; VI_INPUT_DATA_UYVY = 0, 56.

57. ; VI_INPUT_DATA_VYUY, 58.

59. ; VI_INPUT_DATA_YUYV, 60.

61. ; VI_INPUT_DATA_YVYU 62.

63. 64.

65. Vsync =1 ; vertical synchronization signal 66.

67. ;VI_VSYNC_FIELD = 0, 68.

69. ;VI_VSYNC_PULSE, 70.

71. VsyncNeg=0 ;Polarity of the vertical synchronization signal 72.

73. ;VI_VSYNC_NEG_HIGH = 0, 74.

75. ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E 76.

77. Hsync =0 ;Attribute of the horizontal synchronization signal 78.

79. ;VI_HSYNC_VALID_SINGNAL = 0, 80.

81. ;VI_HSYNC_PULSE, 82.

83. HsyncNeg =0 ;Polarity of the horizontal synchronization signal 84.

85. ;VI_HSYNC_NEG_HIGH = 0, 86.

87. ;VI_HSYNC_NEG_LOW 88.

89. VsyncValid =0 ;Attribute of the valid vertical synchronization signal 90.

91. ;VI_VSYNC_NORM_PULSE = 0, 92.

93. ;VI_VSYNC_VALID_SINGAL, 94.

95. VsyncValidNeg =0;Polarity of the valid vertical synchronization signal 96.

97. ;VI_VSYNC_VALID_NEG_HIGH = 0, 98.

99. ;VI_VSYNC_VALID_NEG_LOW 100.

101. Timingblank_HsyncHfb =0 ;Horizontal front blanking width 102.

103. Timingblank_HsyncAct =1280 ;Horizontal effetive width 104.

105. Timingblank_HsyncHbb =0 ;Horizontal back blanking width 106.

107. Timingblank_VsyncVfb =0 ;Vertical front blanking height 108.

109. Timingblank_VsyncVact =720 ;Vertical effetive width 110.

111. Timingblank_VsyncVbb=0 ;Vertical back blanking height 112.

113. Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive) 114.

115. Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive) 116.

117. Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive) 118. 119. 120.

121. ;----- only for bt656 ----------

122. FixCode =0 ;BT656_FIXCODE_1 = 0, 123.

124. ;BT656_FIXCODE_0 125.

126. FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0 127.

128. ;BT656_FIELD_POLAR_NSTD