发布时间 : 星期六 文章基于FPGA的数字电压表设计更新完毕开始阅读a001073b376baf1ffc4fadd4
ADR0 => v55(1), ADR1 => GND, O => v55_1_rt_O );
v55_1_rt_LUT1_L_BUF : X_BUF port map (
I => v55_1_rt_O, O => v55_1_rt );
v44_2_rt_25 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v44(2), ADR1 => GND, O => v44_2_rt_O );
v44_2_rt_LUT1_L_BUF : X_BUF port map (
I => v44_2_rt_O, O => v44_2_rt );
v44_1_rt_26 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v44(1), ADR1 => GND, O => v44_1_rt_O );
v44_1_rt_LUT1_L_BUF : X_BUF port map (
I => v44_1_rt_O, O => v44_1_rt );
v55_3_rt_27 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v55(3), ADR1 => GND,
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O => v55_3_rt_O );
v55_3_rt_LUT1_L_BUF : X_BUF port map (
I => v55_3_rt_O, O => v55_3_rt );
v33_3_rt_28 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v33(3), ADR1 => GND, O => v33_3_rt_O );
v33_3_rt_LUT1_L_BUF : X_BUF port map (
I => v33_3_rt_O, O => v33_3_rt );
v44_3_rt_29 : X_LUT2 generic map( INIT => X\ )
port map ( ADR0 => v44(3), ADR1 => GND, O => v44_3_rt_O );
v44_3_rt_LUT1_L_BUF : X_BUF port map (
I => v44_3_rt_O, O => v44_3_rt );
clk_bufgp_IBUFG_30 : X_CKBUF port map ( I => clk,
O => clk_bufgp_IBUFG );
clk_bufgp_BUFG : X_CKBUF port map (
I => clk_bufgp_IBUFG, O => clk_bufgp
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);
v55_2_GSR_OR_31 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v55_2_GSR_OR );
v44_2_GSR_OR_32 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v44_2_GSR_OR );
v33_2_GSR_OR_33 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v33_2_GSR_OR );
v33_3_GSR_OR_34 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v33_3_GSR_OR );
v33_0_GSR_OR_35 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v33_0_GSR_OR );
v33_1_GSR_OR_36 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v33_1_GSR_OR );
v44_3_GSR_OR_37 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v44_3_GSR_OR );
v44_0_GSR_OR_38 : X_OR2
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port map (
I0 => v33_0_n33, I1 => GSR, O => v44_0_GSR_OR );
v44_1_GSR_OR_39 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v44_1_GSR_OR );
v55_3_GSR_OR_40 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v55_3_GSR_OR );
v55_0_GSR_OR_41 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v55_0_GSR_OR );
v55_1_GSR_OR_42 : X_OR2 port map (
I0 => v33_0_n33, I1 => GSR, O => v55_1_GSR_OR );
v1_3_obuf_GTS_TRI_43 : X_TRI port map (
I => v1_3_obuf_GTS_TRI,
CTL => NlwInverterSignal_v1_3_obuf_GTS_TRI_CTL, O => v1(3) );
v1_2_obuf_GTS_TRI_44 : X_TRI port map (
I => v1_2_obuf_GTS_TRI,
CTL => NlwInverterSignal_v1_2_obuf_GTS_TRI_CTL, O => v1(2) );
v1_1_obuf_GTS_TRI_45 : X_TRI port map (
I => v1_1_obuf_GTS_TRI,
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