发布时间 : 2024/8/31 3:20:35 星期六 文章基于FPGA的数字电压表设计更新完毕开始阅读a001073b376baf1ffc4fadd4

I => GTS,

O => NlwInverterSignal_v4_2_obuf_GTS_TRI_CTL );

NlwInverterBlock_v4_1_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v4_1_obuf_GTS_TRI_CTL );

NlwInverterBlock_v4_0_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v4_0_obuf_GTS_TRI_CTL );

NlwInverterBlock_v5_3_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v5_3_obuf_GTS_TRI_CTL );

NlwInverterBlock_v5_2_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v5_2_obuf_GTS_TRI_CTL );

NlwInverterBlock_v5_1_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v5_1_obuf_GTS_TRI_CTL );

NlwInverterBlock_v5_0_obuf_GTS_TRI_CTL : X_INV port map ( I => GTS,

O => NlwInverterSignal_v5_0_obuf_GTS_TRI_CTL );

NlwBlockROC : ROC generic map ( WIDTH => 100 ns) port map (O => GSR);

NlwBlockTOC : TOC port map (O => GTS); end Structure;

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