发布时间 : 星期六 文章基于FPGA的数字电压表设计更新完毕开始阅读a001073b376baf1ffc4fadd4
(clk=>clk,reset=>reset,eoc=>eoc,D=>D,ale=>ale,start=>start,oe=>oe,clk500k=>clk500k,xs=>xs,Q=>Q_load); u3:yima port map
(clk=>clk,clkz=>clkz_load,Q=>Q_load,v1=>v1_load,v2=>v2_load,v3=>v3_load,v4=>v4_load,v5=>v5_load); u4:lcd port map
(clk=>clk,reset=>reset,dw1=>dw1_load,v1=>v1_load,v2=>v2_load,v3=>v3_load,v4=>v4_load,v5=>v5_load, 按键： library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM;
--use UNISIM.VComponents.all;
entity key is
Port (clk,reset:in std_logic;
architecture Behavioral of key is signal clkk:std_logic; begin
process(clk,reset) variable clk1:std_logic;
variable cnt:integer range 0 to 50000000; begin
if reset='1' then
if clk'event and clk='1' then if cnt<49999999 then
clk1:='1';cnt:=cnt+1;
key1:in std_logic;
clkz:out std_logic;
dw1:out integer range 0 to 2;
cba:out std_logic_vector(2 downto 0));
lcden=>lcden,lcdda=>lcdda,lcdrw=>lcdrw,lcddata=>lcddata); end Behavioral;
end key;
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elsif cnt<=50000000 then clk1:='0';cnt:=0;
end if;
end if;
end if; clkz<=clk1; end process;
process(clk,reset) variable clk0:std_logic;
variable cnt:integer range 0 to 3125000;---0.125s begin
if reset='0' then cnt:=0;clk0:='0'; elsif clk'event and clk='1' then if cnt=3125000 then cnt:=0;clk0:=not clk0; else cnt:=cnt+1;
end if;
end if;
clkk<=clk0; end process;
process(clkk,reset,key1)
variable cnt:integer range 0 to 3; begin
if reset='1' then if rising_edge(clkk) then if cnt>2 then cnt:=0; elsif key1='0' then cnt:=cnt+1; case cnt is
when 1=>cba<=\ when 2=>cba<=\
when others=>cba<=\
end case;
end if;
end if;
end if;
end process; end Behavioral;
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显示； library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM;
--use UNISIM.VComponents.all;
entity lcd is
generic(delay:integer:=100); ---类属说明 Port ( clk,reset:in std_logic; dw1:in integer range 0 to 2;
v1,v2,v3,v4,v5:in integer range 0 to 9;
lcden:out std_logic; --接LCD使能端
lcdda:out std_logic; --接LCD_da信号输入端 lcdrw:out std_logic; --接LCD读写信号输入端
lcddata:inout std_logic_vector(7 downto 0));--接LCD数据输入位 end lcd;
architecture Behavioral of lcd is signal clk_500hz:std_logic;
type state is (set_dlnf,clear_lcd,set_cursor,set_dcb,set_location,write_data); signal current_state:state;
type ram is array(0 to 9) of std_logic_vector(7 downto 0); signal dataram :ram;
signal x1,x2,xv1,xv2,xv3,xv4,xv5:std_logic_vector(7 downto 0); constant v:std_logic_vector(7 downto 0):=\constant g:std_logic_vector(7 downto 0):=\横杠 constant k:std_logic_vector(7 downto 0):=\空格 constant d:std_logic_vector(7 downto 0):=\小数点 constant dw:std_logic_vector(7 downto 0):=\单位v begin
process(clk,reset,clk_500hz)
variable cnt:integer range 0 to 5000;---1khz begin
if reset='0'then cnt:=0;clk_500hz<='0'; elsif clk'event and clk='1' then cnt:=cnt+1;
if cnt<2500 then clk_500hz<='1';
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elsif cnt<5000 then clk_500hz<='0'; else cnt:=0;clk_500hz<='0';
end if;
end if;
end process;
process(clk,dw1) begin
if clk'event and clk='1' then case dw1 is
when 1=>x1<=d;x2<=k;---1 档
when 2=>x1<=k;x2<=d;---10 档
when others=>x1<=\
end case;
end if;
end process;
process(clk,v1,v2,v3,v4,v5) begin
if clk'event and clk='1' then case v1 is when 0=>xv1<=\
when 1=>xv1<=\ when 2=>xv1<=\ when 3=>xv1<=\ when 4=>xv1<=\ when 5=>xv1<=\ when 6=>xv1<=\ when 7=>xv1<=\ when 8=>xv1<=\ when 9=>xv1<=\
when others=>xv1<=\
end case;
case v2 is when 0=>xv2<=\
when 1=>xv2<=\ when 2=>xv2<=\ when 3=>xv2<=\ when 4=>xv2<=\ when 5=>xv2<=\ when 6=>xv2<=\ when 7=>xv2<=\
when 8=>xv2<=\
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