发布时间 : 星期日 文章基于Libero的数字逻辑设计仿真及验证实验实验报告-eda更新完毕开始阅读a31caba6ddccda38366baf03
integer I;
always @(DataIn or EI) begin:local if(EI) begin
Dataout=7; EO=1; GS=1; end
else if(DataIn==8`b11111111) begin
Dataout=7; EO=0; GS=1; end else
for(I=0;I<8;I=I+1) begin
if(~DataIn[I]) begin
Dataout=~I; EO=1; GS=0; end end end
endmodule
//74HC148测试平台代码 `timescale 1ns/10ps module testbench; reg [7:0] in; reg EI;
wire [2:0] out; wire EO,GS;
HC148 testbench148(in,EO,out,EI,GS); initial begin EI=0;#20; EI=1;#20; end initial begin
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in=`b00000001; repeat(9)
#20 in=in<<1; end
endmodule
//74HC138代码
module HC138(DataIn,E1N,E2N,E3,Eq); input [2:0]DataIn; input E1N,E2N,E3; output [7:0]Eq; wire [2:0]DataIn; Integer I;
always @(DataIn,E1N,E2N,E3) begin
if((!E1N)&&(!E2N)&&E3) for(I=0;I<8;I=I+1) if(DataIn==I) Eq[I]=1; else Eq[I]=0; else Eq=0; end
endmodule
//74HC138测试平台代码 `timescale 1ns/10ps module testbench; reg [2:0] in;
reg E1N,E2N,E3; wire [7:0] eq;
HC138 testbench138(in,E1N,E2N,E3,eq); initial begin in=0; repeat(20)
#20 in=$random; end initial begin E1N=1;#40; E2N=1;#40; E3=0;#40; E1N=0;#40;
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E2N=0;#40; E3=1;#40; end
endmodule
//74HC153代码
module HC153(EN,D0,D1,D2,D3,S0,S1,Y); input EN,D0,D1,D2,D3,S0,S1； output Y; reg Y;
always @(EN,D0,D1,D2,D3,S0,S1) begin
if(!EN) case({S1,S0}) 0:Y=D0; 1:Y=D1; 2:Y=D2; 3:Y=D3;
default:Y=1’bx; endcase end
endmodule
//74HC153测试平台代码 `timescale 1ns/10ps module testbench;
reg EN,D0,D1,D2,D3,S0,S1; wire Y;
HC153 testbench153(EN,D0,D1,D2,D3,S0,S1,Y); initial begin EN=1;#50; EN=0;#50; end initial begin
D0=0;D1=0;D2=0;D3=0;S0=0;S1=0; #100 D0=1;D1=0;D2=0;D3=1; #100 S1=0;S0=1; #100 S1=1;S0=0; #100 S1=1;S0=1; #100; end
endmodule
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//74HC85代码
module HC85(DataA,DataB,QAGB,QASB,QAEB,IAGB,IASB,IAEB); input [3:0] DataA,DataB; input IAGB,IASB,IAEB; output QAGB,QASB,QAEB; reg QAGB,QASB,QAEB; always @(DataA,DataB) begin
if(DataA>DataB) begin
QAGB=1;QASB=0;QAEB=0; end
else if(DataA QAGB=0;QASB=1;QAEB=0; end else if(IAGB&!IASB&!IAEB) begin QAGB=1;QASB=0;QAEB=0; end else if(!IAGB&IASB&!IAEB) begin QAGB=0;QASB=1;QAEB=0; end else if(IAEB) begin QAGB=1;QASB=0;QAEB=0; end else if(IAGB&IASB&!IAEB) begin QAGB=0;QASB=0;QAEB=0; end else if(!IAGB&!IASB&!IAEB) begin QAGB=1;QASB=1;QAEB=0; end end endmodule //74HC85测试平台代码 `timescale 1ns/10ps module testbench; 11