发布时间 : 星期一 文章基于FPGA的多通道采样系统设计课程设计论文更新完毕开始阅读a5dca0104531b90d6c85ec3a87c24028915f8596
附 录
1 各模块程序 （1）通道选择模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count is
port(clk:in std_logic;
--cnt:out integer range 0 to 7;
cnt : out std_logic_vector(2 downto 0)); --oc : out std_logic); end count;
architecture archcount of count is signal q:std_logic_vector(2 downto 0); begin
counter:process(clk) begin
if(clk'event and clk='1') then if q=\
q<=\ else
q<=q+1;--oc<='0'; end if; end if;
cnt<=q; end process; end archcount;
（2）延时模块
library ieee;
use ieee.std_logic_1164.all; entity delay is
port(in1,in2,in3:in std_logic;
out1,out2,out3:out std_logic); end delay;
architecture behav of delay is
signal comin:std_logic_vector(2 downto 0); signal comout:std_logic_vector(2 downto 0); begin
process(in1,in2,in3)
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begin
comin<=in3&in2&in1; case comin is
when \ when \ when \ when \ when \ when \ when \ when \ when others=>comout<=\ end case;
out1<=comout(0);out2<=comout(1);out3<=comout(2); end process; end behav;
（3）AD采样控制模块
library ieee;
use ieee.std_logic_1164.all; entity adcontrol is
port(D : in std_logic_vector(11 downto 0);
clk,eoc : in std_logic;
b0,b1,b2:in std_logic;
wr_en,rd_en : out std_logic;
lock0,conv,rd,cs: out std_logic;
Q : out std_logic_vector(15 downto 0)); end entity;
architecture behav of adcontrol is
type states is(st1,st2,st3,st4,st5,st6,st7,st8); signal current_state,next_state:states:=st1; signal regl1 : std_logic_vector(11 downto 0); signal regl : std_logic_vector(15 downto 0); signal lock : std_logic; begin
lock0 <= lock;
com1:process(current_state,eoc) begin
case current_state is
when st1 => next_state <= st2; when st2 => next_state <= st3; when st3 => next_state <= st4;
when st4 => if (eoc='1') then next_state <= st4;
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else next_state <= st5; end if;
when st5 => if (eoc='0') then next_state <= st5; else next_state <=st6; end if;
when st6 => next_state <= st7; when st7 => next_state <= st8; when st8 => next_state <= st1; when others => next_state<=st1; end case; end process com1;
com2:process(current_state) begin
case current_state is
when st1 => conv<='1'；cs<='1'；rd<='1'；lock<='0'；wr_en<='0'；rd_en<='0'；
when st2 => conv<='0'；cs<='1'；rd<='1'；lock<='0'；wr_en<='0'；rd_en<='0'；
when st3 => conv<='1'；cs<='1'；rd<='1'；lock<='0'；wr_en<='0'；rd_en<='0'；
when st4 => conv<='1'；cs<='1'；rd<='1'；lock<='0'；wr_en<='0'；rd_en<='0'；
when st5 => conv<='1'；cs<='1'；rd<='1'；lock<='0'； wr_en<='0'；rd_en<='0'；
when st6 => conv<='1'；cs<='0'；rd<='0'；lock<='1'； wr_en<='1'；rd_en<='0'；
when st7 => conv<='1'；cs<='1'；rd<='1'；lock<='0'； wr_en<='0'；rd_en<='1'；
when st8 => conv<='1'；cs<='1'；rd<='1'；lock<='0'；wr_en<='0'；rd_en<='0'； when others => conv<='1'；cs<='1'；rd<='1'；lock<='0'；wr_en<='0'；rd_en<='0'; end case;
end process com2; com3:process(clk)
variable dog_count:integer range 0 to 64;
variable com3_num_count:integer range 0 to 16553500; begin
if(clk'event and clk='1') then current_state<=next_state; --看门狗
if(current_state=st4) then m_watchdog <= s0; end if;
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if(current_state=st6) then m_watchdog <= s1; dog_count:=0; end if;
if(m_watchdog=s0) then
dog_count:=dog_count+1; if(dog_count>40) then current_state<=st1; dog_count:=0; end if; end if;
--看门狗 end if;
end process com3; latch1:process(lock) begin
if lock='1' and lock'event then regl1<=D; end if;
end process latch1; regl<='0'&b2&b1&b0®l1; Q<=regl1; end behav;
（4）串并转换模块部分程序
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter4 is
port(clk:in std_logic;
cnt4 : out std_logic_vector(3 downto 0) );
end counter4;
architecture archcount of counter4 is signal q:std_logic_vector(3 downto 0); begin
counter:process(clk) begin
if(clk'event and clk='1') then if q=\ q<=\ else
q<=q+1; end if; end if;
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