发布时间 : 星期日 文章东南大学信息学院poc实验报告更新完毕开始阅读bd3b22286cdb6f1aff00bed5b9f3f90f76c64d12
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②After sending character to printer, POC sets the SR7 to 1, which indicates POC is ready to receive another character from the processor. The transfer cycle can now repeat.（① and ② are same with the polling state）
PS: During the handshaking operations between POC and printer, the processor does not try to access POC until it receives the interrupt request signal
3. The overall connection of the simulated printer and POC expressed in the top module form
Figure 3. The top module form of the project
4. Design description of the simulation input waveforms
The input and output of CPU,POC and printer are shown below:
Processorj Pins clk mode Description Input the clock for the CPU running. Choose the mode for printing. When mode=’1’,select a interrupt mode. Receive the interrupt signal IRQ. When IRQ='1' , new data can be sent. Read data from poc. Write data into poc. Show the direction of the DOUT[7..0] and DIN[7..0] When rw='0', read data from POC. When 'rw'='1', write data to POC. Control the address read and write on POC. Input IRQ DIN[7..0] DOUT[7..0] rw Output A0 word资料
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CS When A0='0', choose SR. When A0='1', choose BR. CS=‘1’, poc work. data[7..0] The data send to POC to be printed POC Pins clk Description Input the clock for the POC running. Show the direction of the DOUT[7..0] and DIN[7..0] When rw='0', send data to CPU. When 'rw'='1', read data from CPU. Input address, When A0='0', choose BR. When A0='1', Input the ready signal from printer. When RDY='1', the printer is idle. Input the mode of the POC. When CS=’0’,select a polling mode. When CS=’1’,select a The data receive from CPU to be printed. Output the data to printer. Output the interrupt signal IRQ to CPU, showing the POC and printer is ready. The response to print' RDY signal, a one-cycle pulse at the port TR (transfer request) shows that new data is sent to printer. CS=0 POC send the state of SR to CPU ; CS=1 CPU read the data write in BR The register contains the flags for the POC. When SR(7)='1', it's idle. When SR(7)='0', it's busy. The register holds the value of data to print. RW Input A0 RDY CS data[7..0] PD[7..0] IRQ Output TR DOUT[7..0] Signal SR[7..0] BR[7..0] printer Pins Description Input the clock for the printer running. Input the pulse signal from POC, to show new data is coming. Input the data from POC. Output RDY signal, when RDY='1', it shows printer is waiting for new data. clk Input TR PD[7..0] Output RDY word资料
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5. Simulation results
Connection between cpu and poc
Connection between poc and printer
Here are the explanations of the simulation wave: interrupt mode: 1、In the interrupt mode,mode is always set 1, the print process occures by the IRQ signal from poc.
2、When S(7)=0, IRA send ‘0’ to cpu, it means there is a print requirement and cpu begin to handle it.
3、 In the interrupt process RW and A0 are singals from cpu to poc to control the action of poc.
RW=’1’ and A0=’1’ write data from cpu(D) to poc(BR), means the begin of the interrupt process.
RW=’x’ and A0=’x’ means there is no interrupt requirement .
word资料
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4、After sending datas to BR and set sr to “00000000”, if RDY=’1’, poc give a impulse in TR to make the printer begin to work. After the TR signal we can see that the input RDY signal from the printer change from 1 to 0, which shows that the TR signal really make the printer work.
5、After data of BR has been transmitted into printer, poc set SR to “10000001” itself to indicate that it comes to ready and can get the next print task. 6、Let data plus 1 to indicate the next new print cycle.
6. Conclusion and Discussions
1、As a parallel output controller ,poc module to act as an interface between cpu and printer. Form the simulation wave, we can see that my program meets the designs requirements.
2、I divide the system into three parts, and one top entity. And I use two way to finish the top entity. One is write program with vhdl language and another is create a schematic type file and connect wire.
3、By designing the POC module, I find it helps to learn how to use of quartus and VHDL for design and simulation.The process of designing also teachs me the importantce of figuring out the struc- ture and timing of the task before programming .
Appendix:
The program of processor: library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;
entity processor is port (
clk : in std_logic; IRQ : in std_logic;
DOUT : out std_logic_vector(7 downto 0):=\RW : out std_logic:='0';--0read,1write
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