发布时间 : 星期日 文章东南大学信息学院poc实验报告更新完毕开始阅读bd3b22286cdb6f1aff00bed5b9f3f90f76c64d12
.
A0 : out std_logic:='0';--0sr,1br
DIN : in std_logic_vector(7 downto 0) );
end processor;
architecture Behavioral of processor is
signal data:std_logic_vector(7 downto 0):=\signal mode:std_logic:='1';--默认为中断模式 begin
process(clk) begin
if clk'event and clk='1' then if mode='1' then if IRQ='0' then A0<='1';
RW<='1';--写入数据到BR
data<=data+\代表传输的字符 DOUT<=data; else
A0<='X';
RW<='X';--读入SR的数据 end if; end if; end if;
end process;
end Behavioral;
the program of poc: library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.ALL; use ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;
word资料
.
entity poc is port (
A0 : in std_logic; RW : in std_logic; clk : in std_logic; CS : in std_logic:='1'; RDY : in std_logic;
IRQ : out std_logic:='1';
DOUT : out std_logic_vector(7 downto 0); PD : out std_logic_vector(7 downto 0); TR : out std_logic:='0';
DIN : in std_logic_vector(7 downto 0) );
end poc;
architecture Behavioral of poc is
signal SR : std_logic_vector(7 downto 0):=\signal BR : std_logic_vector(7 downto 0):=\signal count:integer range 0 to 5:=0; type state_type is (s0,s1,s2); signal state: state_type:=s0; begin
process(clk) begin
if clk'event and clk='1' then TR<='0'; IRQ<='1'; case state is
when s0=>----中断请求信号 if SR(7)='1' then IRQ<='0';--中断请求 state<=s1; else IRQ<='1'; state<=s2;--无中断请求 end if;
when s1=>----读入读出选择
if RW='1' and A0='1' then--cpu写入数据到BR BR<=DIN; SR(7)<='0'; state<=s2;
elsif RW='0' and A0='0' then--cpu读入SR的数据 DOUT<=SR;
word资料
.
elsif RW='1' and A0='0' then--cpu写入数据到SR SR<=DIN;
elsif RW='0' and A0='1' then--cpu读入BR的数据 DOUT<=BR; end if;
when s2=>----打印机
if RDY='1' then TR<='1'; PD<=BR; SR(7)<='1'; end if; state<=s0; end case; end if;
end process;
end Behavioral;
the program of printer: library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.ALL; use ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;
entity print is port (
RDY : out std_logic:='1'; TR : in std_logic;
PD : in std_logic_vector(7 downto 0); clk : in std_logic );
end print;
architecture Behavioral of print is
word资料
.
signal count: integer range 0 to 5:=0; signal data: std_logic_vector(7 downto 0); signal ready:std_logic; begin
process(clk,TR) begin
if clk'event and clk='1' then if TR='1' then RDY<='0'; ready<='0'; data<=PD; else
if ready='0' then count<=count+1; if count=5 then RDY<='1'; ready<='1'; count<=0; end if; end if; end if; end if;
end process;
end Behavioral;
connection program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;
entity top is port
word资料